The present invention relates generally to an apparatus and method for digital control systems. More specifically, the invention relates to an apparatus and method for digital control systems, used for example in digitally controlled power amplifier systems, digitally controlled motor control systems, and the like, to minimise and suppress limit cycle behaviour in digital control systems.
Digital control systems are used in a variety of applications and systems such as power amplifier control (PAC) systems, motor control systems and the like. Digital control systems, unlike analogue control systems, can suffer from various problems fundamentally arising from the nonlinearity nature of digital dynamics. Such a problem is limit cycles.
Limit cycling may be caused by the inherent nonlinearity of the system typically introduced by quantisation process performed in digital-to-analogue converters (DAC). Another source of limit cycling in PAC systems occurs when the resolution of the power reference is greater than that of the analogue-to-digital (ADC) resolution. DAC quantisation nonlinearities in closed loop digital control systems used in, for example, radio frequency power amplifier regulation, can result in a periodic behaviour of the power level during the modulation phase. The periodic or cyclic behaviour if unchecked may be so severe to cause the system to fail power-time and the switching and modulation output radio-frequency spectrum specifications, for example, European Telecommunications Standardization Institute (ETSI) 11.10 and 05.05 for Global System for Mobile Telecommunications (GSM) standard.
As greater precision control of digital control systems is required, for example in the precision control of transmitter power amplifier output to meet and comply with Time Division Multiple Access (TDMA) systems such as GSM, there is a need for an apparatus and method to minimise and suppress limit cycle behaviour to meet standard requirements in digital control systems.